The Memory Makers Take the Wheel

TSMC announced plans to increase chip manufacturing prices in the second half of 2026, with its most sought-after 3nm process expected to see price hikes of around 15% . Despite efforts to ramp up wafer production, with monthly output projected between 160,000 to 175,000 units in the second quarter, demand driven by AI technology continues to exceed market expectations . The world's largest foundry just told the AI industry what many suspected: you will pay more, and you will wait longer.

This is not a supply hiccup. IDC called the memory chip crunch "a crisis like no other," while big tech companies are on track to spend a staggering $650 billion in 2026, up about 80% from last year's record . The infrastructure buildout powering AI has hit a wall—not in chip design, but in the physical capacity to manufacture the components that make those chips work. And the companies controlling that capacity are no longer playing defense.

Who Controls the Bottleneck?

HBM is sold out through 2026, with allocations for 2027 already being negotiated, shifting real power in AI infrastructure to the memory makers: Samsung, SK Hynix, and Micron . High-bandwidth memory—the stacked DRAM cubes that sit alongside GPUs in AI accelerators—has become the limiting factor in how fast the industry can scale.

Samsung, SK hynix, and Micron control over 95% of global DRAM production and have systematically reallocated manufacturing capacity toward high-bandwidth memory chips used in AI accelerators, leaving consumer-grade DRAM and NAND flash in critically short supply . BofA estimates the 2026 HBM market to reach $54.6 billion, a 58% increase from the previous year . Goldman Sachs forecasted that HBM demand for custom-ordered, ASIC-based AI chips will skyrocket by 82%, accounting for one-third of the market .

The math is brutal. Nvidia's B300 GPU requires eight HBM chips, each containing 12 individual DRAM dies—meaning a single B300 GPU consumes 96 DRAM dies . Nvidia's Rubin GPU, which recently entered production, comes with up to 288 gigabytes of next-generation HBM4 memory per chip, with HBM installed in eight visible blocks, and that GPU will be sold as part of a single server rack called NVL72, which combines 72 of those GPUs into a single system . A single rack consumes nearly 7,000 DRAM dies. Data centers now consume an estimated 70% of all memory chips produced worldwide , according to IDC.

Goldman Sachs assessed that SK hynix will maintain its dominant position in HBM3 and HBM3E until at least 2026, sustaining a total HBM market share of over 50% . Micron can only meet two-thirds of the medium-term memory requirements for some customers and is sold out for 2026 , according to the company's executive.

Can Chipmakers Outrun the Constraint?

Nvidia's answer has been to accelerate its roadmap. The company's RTX Spark Superchip will debut in laptop and desktop computers from Dell and Lenovo this fall, combining microprocessor and graphics chip built with help from Taiwan's MediaTek to run Microsoft's Windows for Arm operating system . During a keynote at Taiwan's Computex conference, Nvidia CEO Jensen Huang said his company, along with Microsoft, is going to "reinvent the PC" .

AMD is pushing its own annual cadence. In 2025, the AMD Instinct MI350 Series pushed the platform forward with new AI data types and larger-model capacity, and in 2026, AMD plans to advance to the Instinct MI400 Series GPUs based on next-generation CDNA 5 architecture . AMD's Instinct MI325X platform outperformed six OEM submissions using Nvidia's H200 platform by up to 8% in the MLPerf Training v5.0 benchmark , according to the benchmark results.

Intel, meanwhile, has government backing. The U.S. government agreed to acquire a 9.9 percent stake in Intel through an $8.9 billion investment funded by $5.7 billion in remaining CHIPS and Science Act grants and $3.2 billion awarded under the Secure Enclave program . Intel began high-volume manufacturing on its 18A node in late 2025, completing the "five nodes in four years" roadmap, with the first 18A product, Panther Lake for laptops, now shipping .

But none of this solves the memory problem. Both Blackwell and Rubin rely on cutting-edge chip-on-wafer-on-substrate (CoWoS) packaging and high-bandwidth memory stacks that remain capacity-constrained, with an analyst teardown revealing that even in 2025, the limiting factor is often HBM substrate allocation, rather than Nvidia's chip yields .

TSMC is the only company that can manufacture the advanced packaging at scale. TSMC is manufacturing the world's largest 5.5-reticle size CoWoS, with greater than 98% yield in 2026 . The 2026 CoWoS-S generation supports a 5.5x reticle interposer accommodating 12 HBM stacks, while the 2027 CoWoS-R/L generation reaches 9.5x reticle with 16 HBM stacks . TSMC's revenue for May 2026 was approximately NT$416.98 billion, an increase of 1.5 percent from April 2026 and an increase of 30.1 percent from May 2025 .

What Changed This Week

TSMC's announcement of 15% price increases on 3nm processes, despite ramping monthly output to 175,000 wafers, signals that even the world's most advanced foundry cannot keep pace with AI demand . Memory-chip makers are steering capital toward higher-margin HBM chips, creating what IDC calls "a crisis like no other" . The power dynamic in AI infrastructure has shifted from chip designers to the manufacturers who control scarce fabrication and packaging capacity.

What to Watch

Micron is building two fabs in Boise, Idaho, that will start producing memory in 2027 and 2028, and a fab in Clay, New York, expected to come online in 2030 . Even if chipmakers ramp up production, potential relief from the shortage is more than a year away—if not longer . A significant shift is anticipated in 2027, when inference workloads could overtake training as the dominant AI requirement , according to JLL—a transition that could reshape which chips, and which memory configurations, command premium pricing. Until then, the companies with locked-in HBM allocations control the pace of the AI buildout.